Field of the Invention
The present invention relates to a processing device for detecting timing error and value signals and a method for designing typical-case timing using the same, particularly to a device for detecting and correcting timing error and a method for designing typical-case timing using the same.
Description of the Related Art
After integrated circuits arrive, the integrated circuits suddenly become ubiquitous, such as computers, smart phones, smart watches, intelligence household appliances, or digital appliances. The mature technology can greatly change human life. The integrated circuits are divided into digital integrated circuits, analog integrated circuits and mixed-signal integrated circuits.
The digital circuits are affected by variation parameters such as parameter drift of fabrication processes, voltage stability, operation temperature, calculation data, aging or clock jitter. The conventional technology only considers data variation and average efficiency for optimizing typical-case distribution. As a result, the conventional technology began to utilize error detectors. For example, refer to FIG. 1. An error detection circuit 10 of Razor-1 samples data twice. An upper output register 12 has a main clock to obtain a speculation value, and a lower shadow register 14 has a skewed clock to obtain a correct value. Then, the speculation value and the correct value are transmitted to a comparator 16 to determine whether speculation is correct. If the speculation is wrong, a stop signal is sent out to add a cycle for correction. Besides, the error detection circuit 10 of Razor-1 has a problem with short path. Since the shadow register 14 of Razor-1 requires a skew clock to obtain the correct value, it costs shorter time to calculate data paths, which results in the problem with short path. Thus, a buffer is added to overcome the problem. However, the buffer leads to a larger area and high power dissipation. Razor-1 obtains the speculation value at a positive level of one cycle, and obtains the correct value and detects error at a negative level of the identical cycle. The added buffer time equals to a duty cycle of the positive level, which represents error toleration capability of Razor-1.
In addition, the inventor of the present invention disclosed a speculative lookahead (SL) error detection circuit 20 to improve the drawbacks of Razor-1, wherein all the registers use synchronization clocks. Since the registers do not require skew clocks, the registers do not have the problem with short path. The solution is to use two datapath units. A first datapath unit 22 and a second datapath unit 24 controlled by the system calculate alternately. For example, the first datapath unit 22 calculates at the first cycle and obtains a speculation value at the second cycle; and the second datapath unit 24 calculates input values at the second cycle; and at the third cycle, the first datapath unit 22 calculates for two cycles to obtain a correct value. Finally, a comparator 26 compares the correct value with the speculation value to determine whether speculation is correct. If the speculation is wrong, the comparator 26 outputs a stop signal to the system. The system adds a cycle to correct error. The error detection circuit 20 can improve the drawbacks of Razor-1. The error detection circuit 20 is different from Razor-1 using cycles of non-synchronization clocks. The speculative lookahead error detection circuit 20 needs to obtain only specification time of function units to consider the error toleration capability. Since the first datapath unit 22 and the second datapath unit 24 obtain the speculation value at the first cycle, obtain the correct value at the second cycle and compare them to detect error, whereby the error detection circuit 20 has to wait for the correct value to determine whether the speculation value is correct, the efficiency may be limited.
To overcome the abovementioned problems, the present invention provides a device for detecting and correcting timing error and a method for designing typical-case timing using the same, which use transition detectors to determine whether transition of a speculation value occurs, thereby improving efficiency of the whole system.